This invention relates to a method of fabricating a semiconductor memory device, or more particularly to a method of fabricating a trench cell capacitors of a MOS memory device.
Recently, along with the trend of higher degree of integration of MOS memory device, the shrinkage technology has been further advanced, and in order to shrink the memory cell in mega-bits DRAM, a method of opening a recess called trench in the semiconductor substrate and fabricating a capacitor by making use of the inner wall of the recess is being employed.
FIG. 2 shows a conventional manufacturing method of trench cell capacitor of such MOS memory device.
First, as shown in FIG. 2 (a), a p-type epitaxial layer 2 is formed on a surface of a p type semiconductor substrate 1. On the surface of the epitaxial layer 2, a field oxide layer 3 is selectively formed by a wellknown method, and a CVD SiO.sub.2 layer 4 is deposited on the whole surface of the epitaxial layer 2 and on the field oxide layer 3. Next, applying a resist on the surface of the CVD SiO.sub.2 layer 4, the resist is patterned, and the CVD SiO.sub.2 layer 4 is removed by etching to obtain a desired shape (in this example, a square loop shape). Afterwards, using the CVD SiO.sub.2 layer 4 as a mask, a loopshaped trench 5 is formed in the epitaxial layer 2 by anisotropic dry etching, using a etching gas including fluorine (F) or chlorine (Cl) gas. And, the CVD SiO.sub.2 layer 4 used as the mask is removed by etching technique.
Next, as shown in FIG. 2 (b), a shallow N.sup.+ layer 6 is formed by diffusion on the side walls and bottom wall of the loop-shaped trench 5. Furthermore, a dielectric layer 7 is formed on the side walls and bottom wall of the trench 5 and on the surface of the epitaxial layer 2 excluding the field oxide layer 3. Finally, a polycrystalline silicon layer 8 containing phosphorus is formed on the surface of the dielectric layer 7 and on the field oxide layer 3. This polycrystalline silicon layer 8 is formed to fill the inside of the trench 5 entirely.
In this way, a trench cell capacitor using the N.sup.30 layer 6 as a first electrode and polycrystalline silicon layer 8 as a second electrode is formed on the side wall and bottom of the trench 5.
In such conventional fabricating method, however, it is hard to form the trench 5 accurately, especially when the aspect ratio (trench depth/trench width) of the trench 5 is high. For example, in the case of a DRAM with 4M bits or more, the trench 5 is often designed as the trench width of 0.9 to 1.0 micron and depth of about 4.+-.1 microns (in this example, the aspect ratio is 5 or more). When such trench 5 is formed by the anisotropic dry etching, the middle part of the side wall of the trench 5 expands toward the outside of the trench 5 in the process of the etching. This is a so-called "bowing" phenomenon caused by side etching. When the trench 5 is deformed in such a way, it is hard to obtain an expected capacitance.
Besides, when it is continued to dig a trench to a depth of about 4 to 5 microns by anisotropic dry etching, the side walls of the trench 5 are damaged in the process of etching, and a sharp residual damage is formed from the periphery of the bottom of the trench 5 toward into the semiconductor substrate 1. When the side wall is damaged, pinholes are liable to be formed in the dielectric layer 7, and the breakdown voltage of the dielectric layer 7 is reduced. Or when a sharp residual damage is formed at the periphery of the bottom, an electric field is concentrated at this portion, and it becomes difficult to restrict the leakage current between adjacent capacitors.